An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs

Abstract

This paper presents a novel digital calibration technique for pipelined ADCs, which compensates both sub-DAC and interstage gain error. The proposed calibration technique is very efficient comparing to other existing calibration techniques, in which only additions and subtractions are employed in this algorithm, no multiplication and division is included. The simplicity of the calibration makes it very easy to be embedded in the mixed signal system design. The power and area overheads due to the calibration circuit are minimized. An example pipelined ADC is designed to demonstrate this calibration technique. Simulation results show that significant improvements can be achieved with the proposed calibration technique.