An efficient circuit-based SAT solver and its application in logic equivalence checking

Abstract

In this paper, we propose an integrated approach that combines a circuit-based SAT solver (CirSAT) with a technique based on XOR-Majority Graph (XMG) rewriting for logic equivalence checking. CirSAT harnesses circuit information to implement a variety of efficient SAT algorithms on the And-Inverter Graph (AIG). Specifically, we introduce the “AIG-J-frontier” algorithm to minimize unnecessary search space during SAT solving. This algorithm employs the fanout count of logic gates as a heuristic to guide conflict resolution decisions. Furthermore, we present a flexible and efficient two-pointer watching scheme for rapid Boolean constraint propagation. The XMG-based rewriting technique is used to simplify logic networks and accommodate a larger number of high fanout nodes. In experiments using ISCAS’85 and EPFL benchmark suites, our method outperforms CNF-based solvers such as Minisat and Lingeling with a 3.66 speedup. It also exhibits an 8.26 speedup compared to the circuit-based solver QuteSAT and a 5.99 speedup when compared to using the CirSAT solver independently.