An efficient BIST method for non-traditional faults of embedded memory arrays

Abstract

In this work, a built-in self-testing (BIST) method is proposed to detect non-traditional faults of embedded memory arrays for a system-on-chip design. The non-traditional faults include single-cell read-sensitive faults and read coupling faults. The BIST method can efficiently deal with embedded memory arrays spatially distributed on the entire SoC chip. The concept of redundant read-write operations is applied to detect all embedded memory arrays with different sizes simultaneously. The redundant operations do not affect fault coverage of the non-traditional faults. The method has the advantages of low hardware overhead, short test time, and high fault coverage for non-traditional defects.