An efficient architecture of transparent-scan sequences among logic blocks using T-algorithm

Abstract

An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The conventional methodology suffers from problems such as high power consumption, less quality results both in terms of pattern count and fault coverage. In order to overcome above problems a new technique called T-algorithm is proposed. This algorithm reduces the clocking in a circuit and optimizes the testing architecture. The testing architecture consists of Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) blocks. The optimization process is mainly focused on the reduction of clock levels, instead of applying clock pulse to each flip-flop separately, the output taken from the MUX is applied to next flip-flops.