An Efficient Application Mapping for Coarse-Grained Reconfigurable Architectures

Abstract

Coarse-grained Reconfigurable Architectures (CGRAs) are very promising to provide high performance at high power efficiency. Hardware simplicity provides such efficiency, and compiler takes the remaining complexity, particulary application mapping. The task of application mapping consists of data and code mapping onto CGRAs. The mapping procedure has responsible for resolving conflicted requirements between exploiting instruction level parallelism and data parallelism to achieve better performance. In this paper, we describe our experience with developing a practical technique for instruction and data mapping based on a generic CGRA. The proposed technique effectively utilizes the exact knowledge of available routing elements, processing elements, and necessary data as well as future resource and data transfer requirements known only at schedule time.