An Efficient and Fast VLIW Compression Scheme for Stream Processor

Gongli Li,Yingying Hou,Junzhe Zhu

doi:10.1109/access.2020.2985501

Abstract

Stream processor has been widely used in multimedia processing because of the high performance gained by parallelism. In order to achieve higher parallelism, the stream processor employs large width structure of VLIW (very long instruction word, VLIW) and multiple parallelizable instructions are organized into one VLIW. Because the width of VLIW is fixed, there are a large number of empty operations (non-operation, NOP) filled in VLIW, which results in serious code size expansion problem. Aiming at this issue, the horizontal code compression and vertical code compression methods are applied on the VLIW of stream processor respectively. First the VLIW is divided into several subfields according to the logic characteristics of VLIW instruction, then the horizontal code compression scheme which based on Huffman coding is applied on each subfield and this method can achieve approximately 78% code size reduction on average. However, the extra-long time required to decode the compressed VLIW before instruction execution may cause system performance penalty. In order to reduce the decompression time consumption, the vertical compression scheme is proposed. The vertical compression can reduce the code size nearly 70% by deleting the NOPs of VLIW in vertical direction. Furthermore the VLIW after vertical compression can be executed directly without decompression operation by using banked instruction memory. Specifically, the vertical compression can compress stream processor VLIW code size significantly and without any negative influence on performance.

Highlights

The stream processors [1]–[5] have achieved high performance through integrating a lot of parallel function units to develop the parallelism of application and have been successfully used in multimedia processing [6]–[8], mobile devices [9]–[11] and information security [12], [13]
COMPRESSION RATIO In order to analyze the performance of vertical compression scheme, six typical stream applications were mapped to CISP (Its structure can be seen in Figure 1), which is a stream processor prototype with five parallel function units and the vertical compression was applied to the VLIW
This is because vertical compression can delete all NOPs in VLIW, NOPs were filled for storing, and ifnull and profile were added for decompression, the compressed VLIW still achieved more than 50% code size reduction on average

Summary

INTRODUCTION

The stream processors [1]–[5] have achieved high performance through integrating a lot of parallel function units to develop the parallelism of application and have been successfully used in multimedia processing [6]–[8], mobile devices [9]–[11] and information security [12], [13]. In order to increase the compression ratio, at the same time enhance the decoding speed and reduce the impact on system performance after code size compressed, an efficient and fast VLIW compression scheme for stream processor is proposed. The contributions of our work can be concluded as follows: a) After in-depth analysis of VLIW characteristics on stream processor, it is proposed to divide a VLIW instruction into multiple subfields, which can effectively increase the probability of NOPs and improve the compression ratio; b) The horizontal compression and vertical method are both applied to VLIW. In vertical compression, it only deletes NOPs in the vertical direction without changing the structure of the instruction.

VLIW CHARACTERISTICS ANALYSIS

VERTICAL COMPRESSION

CONCLUSION