An efficient address assignment strategy for shared multibuffer ATM switches

Abstract

Shared multibuffer ATM switches are attractive since they can extend memory bandwidth by the use of multiple independent buffer memories. Although the parallel accessibility allows a considerable improvement in memory bandwidth, a proper assignment of memory addresses to cells is necessary to better utilize the potential bandwidth. In this paper, we present an efficient address assignment strategy for shared multibuffer ATM switches. It is based on a combination of two key concepts, uniform distribution for writes and reference locality for reads. The former is to reduce cell loss ratio due to overflow and write access conflicts. The latter is to have cells destined for the same output port read from the same buffer memory to minimize read access conflicts. A single threshold is employed to assign memory locations adaptively depending on the cell distribution among the shared buffer memories. The proposed strategy is shown to out-perform the existing ones, in terms of cell loss ratio, cell delay, and throughput. Moreover, the performance gains have been made with a simple control circuit.