An Efficient Adder Architecture with Three- Independent-Gate Field-Effect Transistors

Abstract

Three-Independent-Gate Field-Effect Transistors (TIGFETs)extend the functional diversity of a single transistor by allowing a dynamic electric reconfiguration of the polarity. This property has been shown to unlock unique circuit level opportunities. In this article, a ripple-carry 32-bit adder is uniquely designed using simulated TIGFET technology and its metrics are compared against CMOS High-Performance (HP)and CMOS Low-Voltage. By adopting TIGFET's polarity control characteristic, the proposed ripple-carry adder architecture uses efficient exclusive OR and majority gates to compute complementary carry signals in parallel, leading to a 38% decrease in logic depth as compared to the standard CMOS design. Additionally, a 38% reduction in contacted gates reduces the effects coming from an interconnect-limited design. The results show that the decrease in the logic depth and the reduction in contacted gates lead to a 3.8x lower energy-delay product and a 5.6x lower area-delay product as compared with CMOS HP. The boost in performance coming from realizing arithmetic circuits with TIGFET transistors makes them a promising next-generation high-performance device technology.