Abstract
As the increasing complexity and scale of FPGA architecture grows, heterogeneity and routability have greatly challenged FPGA placement. In this paper, we propose an effective routability-driven packing algorithm for large-scale heterogeneous FPGAs. First, we present a novel BLE packing method to deal with the complex clock constraints, meanwhile forming more HCLB-friendly BLEs. Then, we propose a congestion-aware HCLB packing technique to produce placement-friendly netlists without degrading routability. Finally, we adopt an effective and accurate method to perform routing congestion estimation to guide the packing algorithm. Based on the ISPD 2017 benchmarks, experimental results show that our algorithm achieves the best overall routed wirelength and outperforms three state-of-the-art FPGA placers by 9.8%, 8.2%, and 3.4% on routed wirelength, respectively.
Published Version
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