An effective iterated greedy algorithm for PCBs grouping problem to minimize setup times

Abstract

The printed circuit boards (PCBs) grouping problem (PGP) is an essential part of PCBs assembly that has attracted much attention in recent years. In this paper, we propose a mathematical model and an iterated greedy (IG) algorithm, called IGP, for solving the PGP with setup time criterion. Based on the problem characteristics, two speed-up theorems are proposed and applied in the IGP. In the IGP, a new solution representation consisting of PCBs assignment sequence and component assignment sequence is adapted, and a heuristic based on PCB pairs and an iterated scheme is presented to create an initial solution. Then a merge operator is introduced to further improve the initial solution. A local search method based on the shift and swap operators is applied to improve solutions from the construction phase. To ensure the diversity of solutions, an acceptance criterion with probability is presented. Additionally, a detailed design experiment is carried out to calibrate the parameters for the presented IGP algorithm. The IGP is assessed by comparing it with the state-of-the-art algorithms in the literature. The experimental results show that the proposed IGP achieves the best performance among the tested methods for PGP.