An effective electrical isolation scheme by iron implantation at different substrate temperatures

Abstract

High-energy implantation of iron in n-type doped InP epilayers at different substrate temperatures: 77K, room temperature (RT), 100/spl deg/C and 200/spl deg/C was investigated to study the electrical isolation of n-type InP. Iron isolation implants were performed at 1MeV with a fluence of 5 /spl times/ 10/sup 14/ /cm/sup 2/. This isolation scheme was chosen to place most of the iron atoms well inside the n-type doped layer. The sheet resistivity (R/sub s/), sheet carrier concentration (n/sub s/) and sheet mobility (/spl mu/) were measured as a function of substrate temperature and post-implantation annealing temperature (100 - 800/spl deg/C). Samples implanted at 77K, RT and 100/spl deg/C show more or less the same trend of post-implant annealing characteristics. A maximum sheet resistivity of /spl sim/1/spl times/10/sup 7/ /spl Omega///spl square/ was achieved for samples implanted at 77K, RT and 100/spl deg/C after annealing at 400/spl deg/C. A lower resistivity of /spl sim/1/spl times/10/sup 6/ /spl Omega///spl square/ was obtained for a 200/spl deg/C implant after annealing at 400/spl deg/C. Lower damage accumulation due to enhanced dynamic annealing is observed for the highest implantation temperature. For 200/spl deg/C substrate temperature, annealing above 400/spl deg/C resulted in a gradual decrease in sheet resistivity to a value close to that of the starting material. But this is not the case for the lower substrate temperatures. The sheet resistivity was increased again for 77K, RT and 100/spl deg/C implant after annealing at 600/spl deg/C. We infer that for 77K, RT and 100/spl deg/C implantation temperatures, the electrical isolation is due to a product of both damage related centers and defects related to the presence of Fe whereas for 200/spl deg/C substrate temperature, we infer that only damage induced compensation removes the carriers. These results show the importance of iron implants as a device isolation scheme.