Abstract

To reduce chip-scale topography variation, dummy fill is commonly used to improve the layout density uniformity. Previous work either sought the most uniform density distribution or sought to minimize the inserted dummy fills while satisfying certain density uniformity constraint. However, due to more stringent manufacturing challenges, more criteria, like line deviation and outlier, emerge at newer technology nodes. This paper presents a joint optimization scheme to consider variation, total fill, line deviation and outlier simultaneously. More specifically, first we decompose the rectilinear polygons and partition fill able regions into rectangles for easier processing. After decomposition, we insert dummy fills into the fill able rectangular regions optimizing the fill metrics simultaneously. We propose three approaches -- Fast Median approach, LP approach and Iterative approach, which are much faster with better quality, compared with the results of the top three contestants in the ICCAD Contest 2014.

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