Abstract
An automatic test pattern generation program (ATPG) is described for large, application-specific integrated circuits (ASICs) designed with a scan path technique. This program was implemented with an improved deterministic test generation algorithm that makes use of a split model for circuit representation and multiple testability heuristics for efficient search. The program can also interface to a hardware accelerator to speed up the test compaction process. >
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
