An autolayout system for a hierarchical i.c. design environment

Abstract

Ideally, the high level language input to a silicon compiler should only contain information relevant to the structure and behaviour of the system specified, abstracting out as much as possible to the physical detail. This can be achieved by autolayout software which computes the placement of components and the routes required by connections, but layouts achieved by present algorithms are not usually as good as those produced by manual designs based on a structured methodology. The extra area required by the connections in a poor layout limits the chip performance as well as increasing the chip size and the placement phase of the process is often a major cause of poor layout. This paper describes work aimed at integrating a layout system with a high level structural design language to provide the layout element of a silicon compiler, and consists of two main areas. Firstly, an autolayout program is described which presently interfaces to a relatively simple cell based hierarchical description language, and secondly moves towards integrating the program with a more advanced language are outlined. The algorithm used for routing has a global phase in which connections are assigned to channels followed by a detailed phase in which the channel space required is evaluated and actual connection paths are determined. The autolayout itself is hierarchical so that advantage can be taken of regularity and structure in the input description and the amount of computation will not become prohibitive in a large design. Work is then described aimed at the use of autolayout in a more sophisticated ‘silicon compiler’ environment where an input language captures the structural, functional and some of the physical aspect of the design. From the autolayout point of view a number of constructs exist to allow composition of parts in a hierarchical manner. These include declarations of connection points and structures of these points, association of points and structures in nets, instantiation of blocks and the relative placement of these instances as well as more usual constructs. The description will be metric free, but a degree of control of the floor plan is possible as a result of the specification of relative placement so that comparatively good layout can be achieved without the necessity to consider the details of the design. Examples are given of both the language and layout.