An Attempt to Improve the Processor Performance by Proper Memory Management for Branch Handling

Abstract

The performanceof the processor is highly dependent on the regular supply of correct instruction at the right time. Whenever a data miss is occurring in the cache memory the processor has to spend more cycles for the fetching operation. One of the methodsused to reduce instruction cache miss is the instruction prefetching,which in turn will increase instructions supply to the processor.The technology developments in these fields indicates that in future the gap between processing speeds of processor and data transfer speed of memory is likely to be increased. Branch Predictor play a critical role in achievingeffective performance in many modernpipelined microprocessor architecture. Prefetching canbe done either with software or hardware. In software prefetching the compiler will insert a prefetch code in the program. In this case as actual memory capacity is not known to the compiler and it will lead to some harmful prefetches. In hardware prefetching instead of inserting prefetch code it will make use of extra hardware and which is utilized during the execution. The most significant source of lost performance when the process waiting for the availability of the next instruction. Thetime that is wasted in case of branch misprediction is equal to the number of stages in the pipeline, starting from fetch stage to execute stage. All the prefetching methods are givenstress only to the fetching of the instruction for the execution, not to the overall performance of the processor. The most significant source of lost performanceis,when the process is waiting for the availability of the next instruction. The time that is wasted in case of branch misprediction is equal to the number of stages in the pipeline, starting from fetch stage to execution stage.This paper we made an attemptto study the branch handling in a uniprocessing environment, whenever branching is identified instead of invoking the branch prediction the proper cache memory management is enabled inside the memory management unit.