An attempt to explain thermally induced soft failures during low level ESD stresses: study of the differences between soft and hard NMOS failures

Abstract

This work focuses on the thermal soft failure mechanism occurring in NMOS transistors during low level ESD stresses. Soft and hard failure modes are both precisely characterized using atomic-force microscope (AFM) technique. Thermally induced soft failures are shown to be the first step of the hard failure mechanism. Furthermore, a strong relationship between both soft and hard failures is revealed. Contrary to what was reported until now, our investigation underlines the presence of two different hot spots during the formation of the large molten silicon filament leading to the disastrous short circuit called hard failure.