An Asymmetric, One-To-Many Traffic-Aware mm-Wave Wireless Interconnection Architecture for Multichip Systems

Abstract

Platform based computing modules such as embedded systems and micro-servers are multichip systems with in-package memory and processing chips. Such systems consist of both one-to-one (unicast) and one-to-many (broadcast/ multicast) traffic patterns. State-of-the-art wired interconnection architectures such as Network-on-Chip (NoC) are specially designed to handle on-chip unicast traffic and cannot mask the high off-chip communication latency caused by the chip-to-chip I/Os in multichip systems. Moreover, with the increase in memory-intensive applications and hence one-to-many traffic in a multichip system, this scenario gets even worse as conventionally one-to-many traffic is handled as multiple unicast traffic in a multihop NoC infrastructure. Consequently, a small proportion of such one-to-many traffic increases energy consumption and message latency significantly for chip-to-chip communication. Therefore, to support such one-to-many traffic, these multichip systems with in-package memory need one-to-many traffic-aware interconnection infrastructure. To address these issues, we propose the design of one-to-many traffic-aware Wireless Network-in-Package (WiNiP) architecture by using a novel asymmetric WiNiP topology and a traffic-aware Medium Access Control (MAC) mechanism. With cycle-accurate simulations, we demonstrate that the proposed WiNiP architecture reduces the energy consumption and latency up to 46.96 and 47.08 percent respectively for multichip data transfer compared to state-of-the-art wired NiPs for application-specific traffic.