An area-efficient FPGA implementation of SKINNY block cipher for lightweight application

Abstract

Recently, a new lightweight block cipher, SKINNY, has been proposed by Beierle et al. in Annual Cryptology Conference 2016. This paper presents an area-efficient FPGA implementation of SKINNY block cipher. In this paper, a new column-serial structure is proposed to speed up SKINNY without compromising its area cost, and the implementation of SKINNY S-box is optimized by utilizing FPGA embedded dual-port block memory to save the logic utilization. The proposed structure has been implemented on Altera's Cyclone V FPGA platform. Implementation results show that our column-serial SKINNY-64 requires 88% reduced area cost compared with round-based implementations and achieves 220% speed up factor compared with bible-serial implementations. In total, our implementation achieves the best area efficiency for FPGA implementation of SKINNY.