An Area-Efficient DAMQ Buffer with Congestion Control Support

Abstract

As the port count of routers in an interconnection network increases rapidly, the amount of buffers within the router chip also increases greatly. To improve the buffer utilization and to reduce the buffer size, the dynamically allocated multi-queue (DAMQ) algorithm is commonly used. However, traditional DAMQ buffer management suffers from high write latency and read latency, and one virtual channel (VC) monopolizes the entire buffer. To address these issues, we propose a fast and area-efficient DAMQ buffer-management algorithm and a novel flow-control mechanism based on credit with congestion-control support. The simulation results show that the new DAMQ algorithm can achieve low latency and prevent one VC from occupying the entire buffer during periods of congestion. Additionally, it can achieve high throughput with a shallow buffer, which leads to a reduced chip area.