An Area Efficient Superconducting Unary CNN Accelerator

Abstract

In superconducting circuits, information is carried by ps-wide, µV-tall, Single Flux Quanta (SFQ) pulses. These circuits can operate at frequencies of hundreds of GHz with orders of magnitude lower switching energy than complementary-metal-oxide-semiconductors (CMOS). However, under the stringent area constraints of modern superconductor technologies, fully-fledged, CMOS-inspired superconducting architectures cannot be fabricated at large scales. Unary SFQ (U-SFQ) is an alternative computing paradigm that addresses these area constraints. In U-SFQ, information is mapped to a combination of streams of SFQ pulses and in the temporal domain. In this work, we propose a U-SFQ Convolutional Neural Network (CNN) hardware accelerator capable of comparable peak performance with state-of-the-art superconducting binary (B-SFQ) approaches in 32× less area. CNNs can operate with 5 to 8 bits of resolution with no significant degradation in classification accuracy. The proposed CNN accelerator effortlessly supports this variable resolution and, for less than 7 bits, yields 5×-63× better performance than CMOS and 15×-173× better area efficiency than B-SFQ.