An area efficient multiplexer based CORDIC

Abstract

In the literature, multiplexer has been proposed for the ASIC implementation of unrolled CORDIC (COordinate Rotation DIgital Computer) processor. In this paper, the efficacy of this approach is studied for the implementation on FPGA. For this study, both non pipelined and 2 level pipelined CORDIC with 8 stages and using two schemes - one using adders in all the stages and another using multiplexers in the second and third stages. A 16 bit CORDIC for generating the sine/cosine functions is implemented using all the four schemes on both Xilinx Virtex 6 FPGA(XC6VLX240) and Altera Cyclone II FPGA(EP2C20F484C7). From the implementation results, it is found that the nonpipelined and pipelined CORDICs using multiplexer requires 1.6, 1.4 times lower area in Xilinx FPGA and 1.8, 1.6 times lower area in Altera FPGA than that using only adders. This is achieved without reduction in speed.