An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor

Abstract

Aiming at electrocardiogram (ECG) monitoring systems for wearable and implantable health-care applications, an ultralow-power and low-cost wavelet-based ECG processor is presented in this brief. This processor can work at subthreshold voltage and further save energy by using voltage overscaling (VOS) and algorithmic noise tolerance (ANT). As to the ANT mechanism, we propose a weighted-average-bilateral-estimation predictor and a two-stage architecture with heterogeneous error detection schemes, which enhance the error resiliency of the ECG processor under VOS and improve its robustness against voltage variations within the subthreshold region. Moreover, we intend to meet the strict area constraint of wearable devices, minimizing the hardware cost of the ECG processor and ANT module by using several area-reduction techniques. A test chip of the proposed processor is fabricated under Taiwan Semiconductor Manufacturing Company Limited (TSMC) 65-nm low power (LP) CMOS technology. Measurement results show that this subthreshold processor consumes 2.28 pJ/cycle at (410 mV, 49.8 kHz), and the proposed ANT scheme can result in only 5% area overhead while leading to 7% power saving by tolerating 17% error rate.