An Area-Efficient Column-Parallel Digital Decimation Filter With Pre-BWI Topology for CMOS Image Sensor

Abstract

This paper presents an area-efficient design of a column-parallel second-order digital decimation filter for a $\Sigma \Delta$ analog-to-digital converter-based CMOS image sensor. By using the proposed pre-bitwise-inversion topology having the same mathematical function, the chip area could be curtailed, where the bit-wise-inversion block, required by the correlated-double-sampling, is moved to the front of the adder. Following such a technique as this, more than six inverters and multiplexers can be reduced. This paper also proposes an adder scheme with only 118 transistors to implement the 13-bit dynamic range integrator. Moreover, the number of MSB cells inside the ripple counter is optimized to balance leakage current and active power consumption. Compared with the prior art, the proposed decimation filter core (without registers) can achieve a reduction of about 24% in transistor count. The proposed design is implemented with a 130-nm standard CMOS process. The total chip area of the digital decimation filter is only $4.5\times 145~\mu \text{m}^{2}$ per column, which is less than half area compared against the prior art. According to the post-layout simulation, the maximum operating frequency is 124 MHz, and the total power consumption, including the filter core and 13-bit registers, is less than 6.35 $\mu \text{W}$ under a typical 50-MHz clock frequency.