Abstract
In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960.
Highlights
The carry-ripple adder is composed of many cascaded single-bit full-adders
We compare the circuit performance with three different architectures, 32-bit carry ripple adder, 32-bit carry select adder, and 32-bit area-efficient carry select adder that is proposed in this paper
As for the transistor count, the transistor count of our proposed area-efficient carry select adder could be reduced to be very close to that of carry ripple adder; the transistor count in the conventional carry select adder is nearly double as compared with the proposed design
Summary
The carry-ripple adder is composed of many cascaded single-bit full-adders. The circuit architecture is simple and area-efficient. The summation result is ready before the carry-in signal arrives; we can get the correct computation result by only waiting for one multiplexer delay in each single bit adder. The duplicated adder in the carry select adder results in larger area and power consumption. By utilizing the multiplexer to select the correct output according to its previous carry-out signal, we can still preserve the original characteristics of the parallel architecture in the conventional carry select adder. In this way, the circuit area and transistor count can be greatly reduced and power delay product of the adder circuit can be greatly lowered. Since an average of 15-20% of the total power is dissipated in glitching, low power can be achieved by reducing the glitches of the circuit [l]
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