An Area-Efficient and Tunable Bandwidth- Extension Technique for a Wideband CMOS Amplifier Handling 50+ Gb/s Signaling

Abstract

This paper reports an area-efficient and tunable bandwidth (BW)-extension technique for a wideband CMOS amplifier to handle very high rate (50+ Gb/s) signaling while keeping a low jitter penalty. We identify its architectural advantages by correlating the performances with the frequency domain (magnitude and group delay (GD) responses) and time domain (impulse and step responses) and comparing them with the existing solutions. Specifically, our technique enables a flexible ac characteristic by introducing a tunable grounded active inductor in the bridged-shunt peaking topology, offering: 1) a high BW enhancement ratio (BWER = $2.65\times$ ); 2) BW-power scalability with small in-band gain variation; and 3) fine tunability of the passband gain without affecting the BW, GD, and power. The experimental prototype is a 65-nm CMOS four-stage differential amplifier occupying just 0.0077 mm2. It delivers a 15-dB gain over a 43-GHz BW with 45-mW power consumption. Small in-band gain variation (0.58 dB) and ripple (1.53 dB) are concurrently achieved with low in-band GD variation (17 to 35.3 ps) and ripple (18.3 ps). The achieved figure of merit of 5.48 [(dc Gain $\times$ BW)/Power] compares favorably with the prior art.