An architecture of an MOS‐LSI speech recognition system using dynamic programming

Abstract

In the past several years, a number of very accurate, isolated word speech recognition systems based on dynamic programming techniques have been designed and tested. However, as these techniques are computationally intensive, commercial systems using dynamic time warping have been costly. We have designed an architecture which exploits the capabilities of custom MOS‐LSI designs to implement a complete speech recognition system. This system would operate in real time using dynamic time warping, yet it would only require 4–5 integrated circuits for a moderate (50–200 word) vocabulary. This system is designed to be expandable so that larger vocabularies can be used by including additional IC's in parallel with the others. The integrated circuits which are required are two custom‐designed chips, a memory IC, and a low‐performance microcomputer for overall control. The custom chips include a front end processor for spectral analysis (currently a switched‐capacitor filter bank) with an endpoint detector, and an IC to implement the dynamic programming algorithm. The architecture of the custom chips has been defined so that adequate performance can be obtained from a standard MOS process. A connected speech recognition algorithm that is based on the use of the above IC's has been developed and will be described. It requires additional processing in the low‐speed microcomputer to perform a second level of dynamic programming.