An architecture level simulation methodology

Abstract

Using the Architecture Design and Assessment System (ADAS), the processor level architecture of an example computer system is first represented as a directed graph. Then, a method of simulating instruction execution as a sequence of data transfers between the nodes of the graph is presented. The simulation methodology provides flexibility in observing the architecture dynamically at the processor level. An example application for functional verification is discussed. Development of techniques to convert programs into node sequences and to assign appropriate delays to the nodes is necessary to further enhance the applicability of the methodology. Functional verification and performance estimation through this approach can instigate early design tradeoffs and reduce system development costs. >