An Architecture For A Unified System Of Coordinated Microcomputers

Abstract

This paper discusses the architecture of the Microprogrammable Controller (MPC), a unified system of 50 coordinated intel 808OA-based microcomputers using a bus for communications. The MPC implements a solution for the problem of coordinating a large array of microcomputers oper -ating in an asynchronous, parallel manner. The MPC architecture provides high performance and fault tolerance. The raw port-to-port transfer rate is 250K bits per second with response time being insensitive to the load on the system. Partial configurations within the MPC are tolerated, and errors in one portion of the system are localized, causing no long term degradation in system performance. The MPC is currently in use as a console controller and communications front end for a system consisting of two large mainframes and 48 consoles. The MPC hardware consists of interface processors, called ports, connected to a demand driven multiple access (DDMA) bus. The DDMA bus is a six-foot long, 16-bit parallel bus with a one microsecond cycle. The bus grants access to the ports on a cycle-by-cycle, rotating priority basis. There are four port types: two types of console ports, serial communications interface ports, and management and coordination ports. Each port contains its own local memory and I/O interface with no global memory attached to the bus. The MPC software consists of multiple, functionally-oriented subsystems. The interport communications (IPC) and system management and coordination (SMC) subsystems will be discussed in some detail. The IPC software provides the basic operating system for the other subsystems of the MPG. IPC is a totally distributed subsystem which enforces a uniform flexible protocol for all port to-port communications within the MPC. SMC is primarily responsible for coordination with the mainframes and provides support for the setup and breakdown of console sessions. This architecture presents a viable solution for a long range of problems involving multipro processing and multiprocessor systems.