Abstract
A computer architecture for an accelerated, parallel, nondeterministic, discrete event simulator is described. The machine is evaluated for accelerating: road traffic simulation. The architecture employs reconfigurable logic, systolic arrays, and a reduction bus to perform microscopic discrete event simulation. The simulator, which achieves a speedup factor of at least 91 over its traffic software counterpart, is fast enough to be practical to municipal traffic management engineers handling road incidents in large metropolitan traffic networks.
Full Text 
Sign-in/Register to access full text options
Sign-in/Register to access full text options 
Paper version not known
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
