An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems

Abstract

This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insensitive systems by Singh and Theobald (2004), and provide a detailed system architecture with the following capabilities and benefits: (i) modules arc stalled only when needed, thereby avoiding unnecessary stalling, (ii) adequate metastability resolution is provided, (iii) handshake interfaces between modules are high-performance and low-latency, i.e., capable of transferring data packets on every clock cycle, (iv) IP cores with large clock distribution delays are correctly handled, and (v) an automated approach is provided for wrapper synthesis from formal specifications. For wrapper synthesis, we have developed an automated tool which accepts interface specifications in a high-level language (Component Wrapper Language, or CWL), and automatically produces gate-level implementations of wrapper circuitry that will correctly and efficiently stall the synchronous modules depending on the availability of I/O channels. An optimization is introduced to reduce the cost of the wrapper circuitry by eliminating "busy waiting." A small set of benchmark examples is also proposed, and synthesis results for the tool are promising.