An Architectural Framework of Snoopy Interconnection for Heterogeneous Cache Systems

Abstract

Single-ISA heterogeneous multi-core architecture which is composed of diverse cores, cache systems and shared bus system is promising technique to achieve higher energy efficiency. However, because heterogeneous multi-core processor (HMP) must be designed and verified each of cores, caches and shared bus system, an effort of implementing HMP is multiplied by the number of kinds of each of components. This limits an amount ofmicroarchitectural diversity of commercial or research products which can be practically implemented. In order to reduce the efforts, many researches have focused on automatic generation of HMP. However, generating of shared bus interconnection with supporting cache coherency mechanism of HMP is one of the major challenge to implement an automatic generation system of HMP because suitable implementation for each cache system is strongly tied its specification and a combination of cache systems is too huge. Nevertheless, hand-design is not realistic to implement HMP. Therefore, a framework which supports and helps to implement bus interconnection with cache coherency is needed for both research and commercial field. This paper proposes a framework of snoop-based interconnection for dealing with heterogeneous cache systems and bus interconnection. As the first step to develop and verify this framework, we implemented an automatic generating system of snoop-based interconnection using FabHetero ported to ARM AMBA4 and ACE protocol and verified the system correctly works.