An Architectural Co-Synthesis Algorithm for Distributed, Embedded Computing Systems

Abstract

This chapter describes a new algorithm for the architectural cosynthesis of embedded hardware and software architectures. The algorithm synthesizes a distributed multiprocessor architecture and allocates software processes to the CPUs in the multiprocessor such that the combined hardware–software (HW–SW) architecture is of minimal cost to meet hard deadlines. Many embedded computers are distributed systems, composed of several heterogeneous processors and communication links of varying speeds and topologies. The chapter describes a new heuristic algorithm that simultaneously synthesizes the hardware and software architectures of a distributed system to meet a performance goal and minimize cost. The hardware architecture of the synthesized system consists of a network of processors of multiple types and arbitrary communication topology; the software architecture consists of an allocation of processes to processors and a schedule for the processes. Most previous work in cosynthesis targets an architectural template, whereas this algorithm can synthesize a distributed system of arbitrary topology. The algorithm works from a technology database that describes the available processors, communication links, I/0 devices, and implementations of processes on processors.