Abstract
A background calibration technique to reduce the spur powers caused by timing skews between the sub-channels of interleaved ADCs is demonstrated. By adjusting the DDS (Direct Digital Synthesizer) phase offset of the digital downconverter, the spur levels are reduced for a range of input frequencies. The SFDR (Spurious-free Dynamic Range) improvement obtained from the proposed technique is applicable to various DDS and input frequencies. Background digital mixing approach is utilized to estimate the timing mismatches between sub-channels. It is demonstrated that it is possible to decrease the spur power levels by more than 15dB by using the proposed technique for some specified input frequency bands and fixed DDS frequencies.
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