Abstract
Soft errors have become a critical challenge as a result of technology scaling. Existing hardening techniques commonly associate prohibitive overhead of performance, area and power. To reach a reliability target at acceptable cost, soft error reliability evaluation of components (gates and flip-flops(FFs)) in a circuit is crucial. In this work, the correlation between the state space of sequential circuits and the soft error vulnerability are analyzed theoretically. And an approximate FF reliability sorting approach based on the circuit state analysis is proposed. It combines the advantage of formal techniques based approaches in completeness and the advantage of simulation based approach in differentiating vulnerability of components, which can help engineers make preliminary vulnerability estimation even when a good workload estimation of the design is unavailable. Experimental results on an implementation of a Space wire end node and several ISCAS'89 benchmark sequential circuits indicate the feasibility and potential scalability of our approach.
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