An approach to realize deep submicron multilevel interconnection using low‐resistance and low‐ϵ materials

Abstract

AbstractThis paper discusses techniques for improving the performance of the multilevel interconnection of deep submicron level feature sizes, through the reduction of diffusion layer resistance, contact resistance, metallization resistance, and decrease in permittivity of interlevel dielectrics, and its global planarization. Silicidation of contact hole becomes insufficient for reducing resistance when the contact hole is extremely miniaturized. Contact between metal layers, i.e., the metallized diffusion area and the metal plug, is preferable. In order to reduce signal propagation ideally in interconnection, both low permittivity dielectrics and low resistance metallization are necessary. For reducing metallization resistance, adoption of Cu metallization is suitable.A high‐temperature Cu dry etching and a passivation technique have been developed to reduce contamination by Cu. To provide globally planarized low‐permittivity interlevel dielectrics, an organic spin‐on‐glass (SOG) material with excellent gap filling and relative dielectric constant lower than 3 was developed. Two‐level, globally planarized interconnection test devices were fabricated by applying CMP using silica slurry and a foamed fluorocarbon polishing pad.