An Approach to Improve Harmonic Attenuation and Stability Performance in Multi-Parallel Inverter System

Abstract

In a multi-parallel inverter system, the grid-tied inverters incorporate the PCC voltage feedforward technique to suppress the effect of low-order grid voltage harmonics on the inverter output current. However, this method is prone to instability issues resulting from inverter-grid interactions, especially under inductive grid conditions along with a power-factor correction capacitor connected at the PCC. A simple solution to overcome the above problem is to provide phase compensation through the voltage feedforward path. This technique can eliminate the negative damping region created by the feedforward loop in the inverter output admittance. But, here instability is addressed at the cost of deteriorating the harmonic attenuation capability offered by the voltage feedforward loop. Therefore, a systematic way of compensating the output admittance to overcome instability and at the same time preserving harmonic attenuation capability for low-order grid voltage harmonics is presented in this paper. Output admittance of the inverter is properly shaped by understanding the phasor movement of quantities in the inverter admittance. Finally, it will be shown that a trade-off exists in addressing harmonic instability and harmonic attenuation. As a result, both these problems should be addressed simultaneously. The above findings are validated through hardware prototype and MATLAB simulation results.