Abstract
Symbolic Model Checking is one of the most efficient formal verification methods for hardware design. It uses Computational Tree Logic (CTL) for expressing formal specification of hardware design. However, the large demands of space by Symbolic Model Checking prevents itself from verifying large automates. In this paper we study the possibility of hierarchy evaluation of CTL formula. The result shows that CTL specifications for whole automata can be decomposed into local properties in some case, each of them can be verified on different subautomates respectively. By this way symbolic model checking can be completed hierarchically, which enable us to handle much larger circuits without a large growth of complexity.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
