An approach to automatic test pattern generation using strictly digital neural networks

Abstract

The authors present a parallel algorithm for finding a set of diagnostic patterns to test logic circuits using strictly digital neural networks (SDNNs). They use a new logic circuit called neural logic gate (NLG) to provide two logic functions, and obtain a preliminary set of test patterns. A circuit of the NLG is defined as intersecting sets of neurons with the k-out-of-n design rule, and has neither analog parameters nor stochastic operations. A problem is presented for test pattern generation using NLG to be solved by the SDNN system. The simulation results of automatic test pattern generation for a n-bit full-adder circuit up to 128 bit show that the order of computation is approximately O(n/sup 1.4/) in parallel convergence, and O(n/sup 2.4/) in sequential simulation. Compared with the original neural network, SDNN was able to find a set of test patterns more readily than the original neural network in large scale problems. >