An Analyzable On-Chip Network Architecture for Embedded Systems

Abstract

The increasing integration level of modern and forthcoming Integrated Circuits (ICs) allows the implementation of complex systems on a single chip (System-on-Chip – SoC) [1]. To reduce time to market in the design flow of chip development prefabricated components (known as Intellectual Property – IP) are used. IP cores can be CPUs, memory blocks, signal processing units, etc. Simplified, the design of new complex customized ICs often represents a composition of IP cores. The main task of a chip designer is the selection, parameterization, and interconnection of the different cores. Currently, the interconnection between the IP cores are realized with either dedicated point-to-point interconnections or standardized system buses. Dedicated point-to-point connections are only manageable and economically feasible in smaller systems. With increasing complexity, it is not possible to connect every core with dedicated wires. Buses, on the other hand, are an example for shared communication resources. The system design with a standardized bus and IP cores with an interface to the bus in question, becomes much simpler. Examples for on-chip buses are IBM Core Connect, AMBA-Bus by ARM, and the VCI-Standard by the VSIA. However, as a drawback, buses are not scalable for larger designs. The communication between cores becomes the performance bottleneck of the system. SoC design tends to replace buses with packet-switched interconnection networks [5]. The architecture of switched on-chip networks are similar to