Abstract
Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1−xGex/relaxd Si1−yGey(s-Si/s-SiGe/Si1−yGey) metal-oxide-semiconductor field-effect transistor (PMOSFET), analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si), because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1−yGey metal-oxide-semiconductor field-effect transistor (MOSFET) designs.
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