An Analysis of Solder Joint Formation and Self-Alignment of Chip Capacitors

Abstract

An energy-based 3-D model was created to simulate the solder joint formation of the chip capacitor during reflow. The surface tension (Fs) and hydrostatic force (Fh) of molten solder and the gravitational force (Fg) of a chip capacitor and solder paste were considered in this 3-D model. The initial geometry of solder joint is evolved into an equilibrium shape to minimize the internal energy of molten solder. In this study, we investigated the effect of various design parameters, such as solder paste volume, copper pad dimension, and component height on the solder joint shape of capacitor. Chip capacitor C1005 and C0603 with SAC305 solder paste and copper pads with electroless nickel immersion gold (ENIG) surface finish were used as examples. Actual capacitor samples were cross-sectioned and inspected to validate the simulation results from the 3-D model. Moreover, the self-alignment of the chip capacitor was studied in this work. The component self-alignment will affect the accuracy of component assembly and significantly affects the chip capacitor solder joint formation. Simulations were performed to address the mechanism of chip capacitor self-alignment during reflow soldering. The effect of solder paste volume on the capacitor self-alignment was summarized. The result showed relatively more solder paste that can improve the capacitor self-alignment because of the bigger restoring force generated by the molten solder. The inconsistency of solder paste volumes at the two terminations will cause the capacitor to offset from the center. It is found that the misalignment of capacitor C1005 can be reduced to ±30 μm in component-length direction and ±30 μm in component-width direction by the optimization of solder paste volume. The self-alignment is better in component-width direction than component-length direction. An extensive number of experimental studies were performed to develop a data-driven prediction model so that the manufacturing cost during trial tests can be reduced. In the experiments, the chip capacitors were placed intentionally with some initial offsets and their positions were measured before and after the reflow. Simulation results showed good agreement with the experimental data.