An Analysis of DCM-Based True Random Number Generator

Abstract

A true random number generator (TRNG) using Digital clock manager (DCM) blocks of a Xilinx FPGA has advantages of minimal usage of logic elements and tunability of clock frequencies to search for better randomness. Its operating principle is beat frequency detection, which uses the least significant bits (LSBs) of a counter that counts the number of successive logic-ones captured by a D flip-flop. In this brief, we evaluate the DCM-based TRNG with 100 frequency pairs. The findings of this brief include: 1) only 12 frequency pairs passed the diehard statistical tests when three LSBs were extracted as directed in the previous work; 2) the value of the counter exhibits biphasic histograms; 3) small counter values show less uncertainty; and 4) the number of frequency pairs that passed the tests was doubled to 24 by extracting only one LSB from small counter values, with a 16.9% reduction in the generation rate.