An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

Abstract

In VLSI interconnects, buffers are used to restore the signal level affected by the parasitic such as line capacitance, inductance, etc.. However buffers have a certain switching time that contributes to overall signal delay. Further, transitions that occur in interconnects give rise to crosstalk delay. Thus the overall delay in interconnects is due to the combined effect of both buffers and the crosstalk delay. In this work, replacement of buffers with Schmitt trigger is proposed for signal restoration. Since the threshold voltage of Schmitt trigger can be designed to be lower than that of buffer, signal can rise early while a large noise margin of Schmitt trigger helps in reducing the noise glitches due to crosstalk. Simulation results show that the Schmitt trigger approach gives 20% delay reduction as compared to 10.4% in case of buffer.