An all digital spread spectrum processor featuring multiplier free zero-IF down-conversion, decimation and multiplexed despreading

Abstract

In direct-sequence spread spectrum receivers, complete detection of the modulated-spread signal after RF downconversion consists of IF-carrier and PN-code wipe-off procedures. In the widely used conventional method, the carrier wipe-off is performed using high frequency numerically-controlled oscillators (NCOs) being clocked at rates which are at least 2 times the highest frequency in the IF spectrum. This can mead to large power consumption, especially in multi-channel receivers. On the other hand, in these receivers, faster and more reliable coarse acquisition/reacquisition requires parallel correlation, while for tracking more than one channel of DS/SS data in many spread spectrum applications (e.g. GPS), we must duplicate or multiplex the correlators. This paper describes the design of a multiplier-free all digital quadrature mixer followed by a low power multiplexed multi-phase 12-channel parallel passive correlator and their comparison to some existing architectures. It is also showed that combining multiplexing, parallel passive features and the introduced mixer enables us to implement simple circuits to reduce the power consumption of the baseband receiver as much as possible. The architecture is used to design the first mixer and correlator section of a multi-channel GPS receiver baseband and is fully implemented and tested in an FPGA.