An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience

Abstract

A new, all-digital on-chip peak-to-peak (p-p) jitter measurement circuit (OCJM) that features automatic resolution calibration for high PVT-variation resilience without a reference clock and off-line calibration is presented in this paper. The OCJM uses a front-end self-referenced circuit (SRC) to eliminate the jitter-free reference signal and a back-end p-p jitter detector (PPD) to perform p-p jitter measurements. The key design of the proposed OCJM is that the SRC and the PPD share a Vernier delay line (VDL) so that the run-time PVT information automatically extracted from the SRC operation can be carried onto the PPD to achieve automatic on-line resolution calibration. Besides this feature, the OCJM uses on-chip direct p-p jitter measurement with only 1-time readouts to eliminate the huge power consumption of the off-chip data communication while avoiding data loss of a possible large jitter caused by PVT variations during off-chip data communication. These techniques make the proposed OCJM suitable for any-time, any-site jitter measurements for SoC applications. The proposed OCJM is fabricated in a 28-nm CMOS. The measurement results show that the timing resolution and minimum measurable jitter range specifications are met under extreme PVT conditions while achieving 98% clock cycle and energy reduction compared to the conventional OCJM designs.