An algorithm-driven processor design for video compression

Abstract

A design approach for video signal processors is presented that is driven by characteristics of the algorithms, rather than by technological enhancements to conventional microprocessor-style DSP architectures. The goal of this algorithm-driven approach is the design of processors that possess not only the flexibility to execute several algorithms, but an order of magnitude lower complexity than conventional processors. This design approach is applied to the design of a high-speed signal processor targeted at video compression algorithms including the 8/spl times/8 DCT, wavelet/subband coding, and vector quantization. The fabricated processor chip can execute each algorithm at up 25 MPixels/sec and has been implemented with only 80,000 transistors in a 1.2-/spl mu/m CMOS process. >