An algorithm to design floating field rings in SiC and Si power diodes and MOSFETs

Abstract

Prior work on Silicon Carbide (SiC) power devices has been silent on the exact procedure to be employed for designing the Floating Field Rings (FFRs) meant for raising avalanche breakdown voltage of these devices. On the other hand, prior procedures for designing FFRs in Si devices do not work for kV range breakdown associated with SiC devices, and employ 10’s of μm long rings. We propose a systematic procedure for deriving the number and spacing of the FFRs of any ring length required for achieving an arbitrary breakdown voltage. The procedure can be adapted to implement any one of the ring spacing strategies, namely - constant, decreasing or increasing as one moves outward from the main junction. The procedure is demonstrated for the linearly increasing ring spacing case using TCAD simulations, considering 1.7–5.5 kV 4H-Silicon Carbide devices and a 700 V Si device reported in literature. The FFR structures resulting from our procedure are found to have a total length which is 24.5–75% of that published in literature, and breakdown voltage which is more than 92% of the plane parallel value.