An AES Implementation with Improved PDL Based PUF Key Generator for IoT Devices

Abstract

In recent days, cryptographic algorithm hardware is the need of IoT devices. However, limited resources demand an efficient approach towards designing the said cryptographic algorithm hardware. This paper introduces the PUF (Physical Unclonable Function) based approach to design the key generator used in cryptographic algorithm hardware to minimize the area and power consumption. A customizable key generation unit has been introduced in the form of a Standard Synchronization Unit (SSU) to match the desired key size requirements. The results were generated with PUF based designs from literature and compared with the proposed PDL (Programmable Delay Logic) PUF. All parameters considered, a proposed PDL PUF key generator is an efficient option that can be integrated with an Advanced Encryption System (AES) as the key generator. The modified AES design result was compared with the literature's results on the Xilinx Virtex XC7VX690T platform. The modified AES is an efficient solution with 12.10% less area consumption and a 44.51% increase in throughput.