An advanced area scaling approach for semiconductor burn-in

Abstract

In semiconductor manufacturing, early life failures are avoided by putting the produced items under accelerated stress conditions before delivery. The products’ early life failure probability p is assessed by means of a burn-in study, in which a sample of the stressed items is investigated for early failures. The aim is to prove a target failure probability of the produced devices and release stress testing of the whole population. Given the failure probability level on a reference product, the failure probabilities of so-called follower products with different chip sizes are then obtained by means of area scaling. Classically, area scaling is done with respect to the whole area of the chips. Nevertheless, semiconductors can be partitioned into different chip subsets, which can have different likelihoods of failures. In this paper, we propose a novel area scaling model for the chip failure probability p, which enables us to scale the chip subsets separately from each other. The main idea is to adapt the classical estimators of the failure probabilities of the chip partitions according to the number of failures on the different chip subsets. This leads to a more appropriate estimation of the failure probabilities of the follower products and helps to improve the efficiency of burn-in testing.