An adaptive Viterbi decoder based on FPGA dynamic reconfiguration technology

Abstract

The Viterbi algorithm is the most popular decoding algorithm in communication systems, but its hardware complexity increases in the order of 2/sup k/ with the constraint length K. This work proposed an improved Viterbi algorithm, called adaptive Viterbi algorithm (AVA), only keeping some of the best or most-likely states, so as to reduce the amount of computations and storage memories needed. Using run-time dynamic reconfiguration technology, the parameters of the decoder can be dynamically reconfigured in response to channel noise. Simulation results and careful analysis of the decoder stucture demonstrate that total dynamic reconfiguration technology can be used to improve performance of adaptive Viterbi decoder. Comparison with one Viterbi decoder that has implemented in Xilinx FPGA by us, it is also shown that adaptive Viterbi decoder can save hardware resources by 20%.